Rapid Prototyping with Field Programmable Gate Arrays

Primary Faculty Mentor’s Name

Angkul Kongmunvattana

Proposal Track

Student

Session Format

Paper Presentation

Abstract

This presentation discusses the prototyping process of a circuit board designed to carry out the SubBytes transformation of the Advanced Encryption Standard(AES)[1]. This Standard is an encryption algorithm that is widely used by the information security industry. AES uses the Rijndael cipher, which contains ten rounds of four transformations to scramble the information in order to keep it secure[1]. According to the National Institute of Standards and Technology, “The SubBytes Transformation is a non-linear byte substitution that operates independently on each byte of the State using a substitution table [1].” Ordinarily, encryption of information is done using software implementations of the various encoding processes. However, a hardware implementation is ideal when the goal is making a more efficient use of computing resources and an improved speed of the encryption process. For this project, I designed a circuit board that performs the SubBytes transformation utilizing a prototyping board with field a programmable logic device. A Field Programmable Gate Array is such a device that can have its logic configured by an end user to carry out whatever logical operation the user may choose. I used the Altera Quartus circuit design software in concert with the FPGA prototyping board from Terasic. The circuit takes in 8 bits of input that make up a binary representation of a character. This circuit board uses read-only memory to access a lookup table that contains the given character’s substitute character, which is calculated by the cipher key. By early November, the design will be applied to a circuit board that will carry out all of the Advanced Encryption Standard processes, and analyzed for efficiency. The analysis will determine ways in which the circuit board can be optimized to a faster speed and a lower consumption of resources by reducing the amount of logic gates necessary to carry out the encryption while maintaining the standards put forth by the Advanced Encryption Standard.

References

1. Announcing the Advanced Encryption Standard (AES). Gaithersburg, MD: Computer Security Division, Information Technology Laboratory, National Institute of Standards and Technology, 2001. 26 Nov. 2001. Web. 1, 15.

Keywords

FPGA, Encryption, Prototyping, Circuit design

Award Consideration

1

Location

Room 1909

Presentation Year

2014

Start Date

11-15-2014 1:45 PM

End Date

11-15-2014 2:45 PM

Publication Type and Release Option

Presentation (Open Access)

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Nov 15th, 1:45 PM Nov 15th, 2:45 PM

Rapid Prototyping with Field Programmable Gate Arrays

Room 1909

This presentation discusses the prototyping process of a circuit board designed to carry out the SubBytes transformation of the Advanced Encryption Standard(AES)[1]. This Standard is an encryption algorithm that is widely used by the information security industry. AES uses the Rijndael cipher, which contains ten rounds of four transformations to scramble the information in order to keep it secure[1]. According to the National Institute of Standards and Technology, “The SubBytes Transformation is a non-linear byte substitution that operates independently on each byte of the State using a substitution table [1].” Ordinarily, encryption of information is done using software implementations of the various encoding processes. However, a hardware implementation is ideal when the goal is making a more efficient use of computing resources and an improved speed of the encryption process. For this project, I designed a circuit board that performs the SubBytes transformation utilizing a prototyping board with field a programmable logic device. A Field Programmable Gate Array is such a device that can have its logic configured by an end user to carry out whatever logical operation the user may choose. I used the Altera Quartus circuit design software in concert with the FPGA prototyping board from Terasic. The circuit takes in 8 bits of input that make up a binary representation of a character. This circuit board uses read-only memory to access a lookup table that contains the given character’s substitute character, which is calculated by the cipher key. By early November, the design will be applied to a circuit board that will carry out all of the Advanced Encryption Standard processes, and analyzed for efficiency. The analysis will determine ways in which the circuit board can be optimized to a faster speed and a lower consumption of resources by reducing the amount of logic gates necessary to carry out the encryption while maintaining the standards put forth by the Advanced Encryption Standard.

References

1. Announcing the Advanced Encryption Standard (AES). Gaithersburg, MD: Computer Security Division, Information Technology Laboratory, National Institute of Standards and Technology, 2001. 26 Nov. 2001. Web. 1, 15.